klapauzius
Well-known member
I ran the blink and many of the others already. So I will start playing with the CAN library.
garygid said:I posted a copy of a CAN library and a Timer library, for convenience.
The 4 CAN examples compile, and the 3 Timer examples work.
However, it seems possible to lose timer "handler" executions
in some circumstances, when the executions are scheduled
while another handler is working, perhaps?
garygid said:CAN Transceivers, 3.3v types:
from Mouser, the 595-SN65HVD234DR is the TI SN65HVD234D (R = on reel or tape).
http://www.mouser.com/ProductDetail/Texas-Instruments/SN65HVD234DR/?qs=sGAEpiMZZMsGqoCZrYwANjBlzIePRaFK1g9OIHjKooM%3d" onclick="window.open(this.href);return false;
The 230, 231, and 232 are one series, and the 233, 234, and 235 seem
to be a slightly more "rugged" series of transceiver chips.
I just ordered some SN65HVD234D and SN65HVD235D, but
another member is using the SN65HVD230D (less expensive,
but with fewer features).
The Android Due is currently "supporting" the SN65HVD234D, I believe.
1. My experiments with the Timer examples appeared to demonstrate that
[some] expected timer-end "ticks" ([when the] end of the timer period should activate
the assigned handler routine) could get "lost" (handler not activated).
garygid said:1. My experiments with the Timer examples appeared to demonstrate that
[some] expected timer-end "ticks" ([when the] end of the timer period should activate
the assigned handler routine) could get "lost" (handler not activated).
Reproduce the problem,
Discover the cause,
Design a good fix, if possible.
garygid said:PWM frequency on the order of 10k to 20k, with the 16-bit precision,
or as close as one can get with a 84 MHz / N clock,
and the pulse width controllable to one bit precision.
Since an ADC "fault" can put the PWM section into a "fail-safe" (perhaps
frozen) mode, this part of the function must be understood and controlled.
The Datasheet for the uP chip is only 1467 pages long.
garygid said:Good Work.
The 84 MHz divided by 10 kHz = 8400, and 20 kHz = 4200 clock counts.
We are currently using near 14 kHz, I believe, which would be 6000 clock counts.
Since 12 bits gives one 0 through 4095 we would want the 16 bit
PWM mode to use the 0 to 5999 period counter for 14 kHz
(or slightly less for slightly faster than 14 kHz).
Then, being able to set the PWM pulse width count directly from
from 0 (off) through about 5000 or so should do the trick.
With this we will get about 6 times the resolution that we had
on the AVR-CAN, with its 10-bit counter and 16 MHz clock.
garygid said:With the problems that some have reported with the Due board,
we might need to use something else instead, perhaps the Mbed?
Its libraries are probably more mature, and the architecture
of the chip less convoluted.
Enter your email address to join: